Technique for extended idle duration for display to improve power consumption

ABSTRACT

A method and system for operating in a single display mode operation and a dual pipe mode of operation is disclosed. The method and system includes operating in a dual pipe mode of operation in which each display pipe transmits data from a respective buffer to an associated display. The method and system further includes operating in a single display mode of operation in which one display pipe transmits data from a plurality of buffers to an associated display.

CROSS REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. Pat. Application Serial No.17/390,479, filed Jul. 30, 2021, which is incorporated by reference asif fully set forth.

BACKGROUND

Computing hardware consumes a large amount of power. Mobile devices thatrely on batteries to supply this power benefit from power reduction interms of increased operating duration. Power consumption concerns arethus a perpetual area for improvement for computing hardware.

BRIEF DESCRIPTION OF THE DRAWINGS

A more detailed understanding can be had from the following description,given by way of example in conjunction with the accompanying drawingswherein:

FIG. 1 is a block diagram of an example device in which one or morefeatures of the disclosure can be implemented;

FIG. 2 illustrates a device that is an example implementation of thedevice of FIG. 1 ;

FIG. 3 is a block diagram of the display controller illustratingadditional detail;

FIG. 4 is a block diagram that illustrates the display controller 206operating in an expanded buffer mode, according to an example; and

FIG. 5 is a flow diagram of a method for operating a display controller,according to an example.

DETAILED DESCRIPTION

A disclosed technique includes transmitting data in a first bufferassociated with a first display pipe to a first display associated withthe first display pipe; transmitting data in a second buffer associatedwith a second display pipe to the first display; requesting wake-up ofan external memory that is external to the first display pipe and thesecond display pipe; and refilling one or both of the first buffer andthe second buffer from the external memory.

FIG. 1 is a block diagram of an example device 100 in which one or morefeatures of the disclosure can be implemented. The device 100 caninclude, for example, a computer, a gaming device, a handheld device, aset-top box, a television, a mobile phone, server, a tablet computer orother types of computing devices. The device 100 includes a processor102, a memory 104, a storage 106, one or more input devices 108, and oneor more output devices 110. The device 100 can also optionally includean input driver 112 and an output driver 114. It is understood that thedevice 100 can include additional components not shown in FIG. 1 .

In various alternatives, the processor 102 includes a central processingunit (CPU), a graphics processing unit (GPU), a CPU and GPU located onthe same die, or one or more processor cores, wherein each processorcore can be a CPU or a GPU. In various alternatives, the memory 104 islocated on the same die as the processor 102, or is located separatelyfrom the processor 102. The memory 104 includes a volatile ornonvolatile memory, for example, random access memory (RAM), dynamicRAM, or a cache.

The storage 106 includes a fixed or removable storage, for example, ahard disk drive, a solid-state drive, an optical disk, or a flash drive.The input devices 108 include, without limitation, a keyboard, a keypad,a touch screen, a touch pad, a detector, a microphone, an accelerometer,a gyroscope, a biometric scanner, or a network connection (e.g., awireless local area network card for transmission and/or reception ofwireless IEEE 802 signals). The output devices 110 include, withoutlimitation, a display, a speaker, a printer, a haptic feedback device,one or more lights, an antenna, or a network connection (e.g., awireless local area network card for transmission and/or reception ofwireless IEEE 802 signals).

The input driver 112 communicates with the processor 102 and the inputdevices 108, and permits the processor 102 to receive input from theinput devices 108. The output driver 114 communicates with the processor102 and the output devices 110, and permits the processor 102 to sendoutput to the output devices 110. It is noted that the input driver 112and the output driver 114 are optional components, and that the device100 will operate in the same manner if the input driver 112 and theoutput driver 114 are not present.

FIG. 2 illustrates a device 200 that is an example implementation of thedevice 100 of FIG. 1 . The device 200 includes a memory 202 (which, insome embodiments, is the memory 104 of FIG. 1 ), a data fabric 204, adisplay controller 206, and a power state controller 208. The device 200also includes additional logic 212, such as one or more executionpipelines, cache memories, input/output systems, or other components.

The memory 202 includes one or more memory devices, such as main memory(e.g., memory 104) or other memories. The data fabric 204 is a set ofcircuits that transfers data between various elements of the device 200,such as between the memory 202 and the display controller 206. Thedisplay controller 206 fetches display data such as pixel color valuesand provides that data to the display 210. The display 210 displays thepixel color values provided by the display controller 206, controllingdisplay circuitry to emit specified colors according to the colorvalues. To display images, the display 210 displays a series of frames.The display controller 206 provides sufficient pixel data for individualframes to be displayed. In some modes of operation, the displaycontroller 206 provides pixel information for all pixels of each frameto the display 210, and the display 210 displays the correspondingpixels. In other modes of operation, the display 210 is capable ofperforming a self-refresh function, in which the display 210 repeats thecontents of a frame one or more times, reducing the need for datatransfer from the display controller 206 to the display 210.

The power state controller 208 is capable of controlling the power stateof one or more portions of the device 200. Different portions of thedevice 200 are capable of being set to different power statesindividually. A power state includes a definition of the degree to whicha portion of the device 200 is powered on or off. In some examples, aportion of the device 200 has differing capabilities depending on whichpower state the device 200 is in. In an example, the display controller206 is capable of being placed into a first power state in which thedisplay controller 206 is capable of transmitting pixel data to thedisplay 210, and the display controller 206 is also capable of beingplaced into a second power state in which the display controller 206 isnot capable of transmitting pixel data to the display 210. The differingcapabilities in differing power states trade capability for powerconsumption. Specifically, by switching off one or more components of aportion of the device 200, the capabilities associated with thatcomponent are disabled, but the power that would normally be used bythat component is not expended.

The data fabric 204 and memory 202 are also capable of being powered toa powered-up state or a powered-down state. In the powered-up state, thememory 202 is capable of responding to read or write operations,transmitting data stored therein to a requestor in response to a readrequest and/or storing data into the memory in response to a writerequest. In the powered-down state, the memory 202 is not capable ofresponding to such requests. In the powered-up state, the data fabric204 is capable of transmitting data between endpoints of the data fabric204 (such as the memory 202 and the display controller 206). In thepowered-down state, the data fabric 204 is not capable of transmittingsuch data. That different portions of the device 200 are independentlyswitchable into different power states means that any such portion iscapable of being in a particular power state (e.g., powered up) whileanother such portion is capable of being in a different power state(e.g., powered down). Thus, for example, it is possible for the powerstate controller 208 to be powered up while the data fabric 204 and/ormemory 202 are powered down. It is also possible for the displaycontroller 206 to be powered up or down regardless of whether the datafabric 204 and/or memory 202 are powered up or powered down.

The power state controller controls the power states of the differentportions of the device 200. In general, the power state controller 208controls these power states according to inputs from a variety ofplaces, such as hardware units within the device 200 or software modulesexecuting on a processor such as an operating system or driver. In someexamples, where the device 200 is sufficiently idle (e.g., no user inputhas been received recently, and a central processing unit is powereddown), the power state controller 208 places the device 200 into a powermode referred to herein as a “display stutter” power mode. In thedisplay stutter power mode, the display controller 206, memory 202, anddata fabric 204 are placed into a low power state. One or more portionsof the additional logic 212 are optionally also placed into the lowpower state. The power state controller 208 powers up the displaycontroller 206, memory 202, and data fabric 204 in the situations thatthose components are needed, as described in further detail herein.

An example sequence of operations for the display stutter power mode isnow described. The sequence begins in a state in which the displaycontroller 206 is powered up and the data fabric 204 and memory 202 arepowered down. The display controller 206 includes a buffer 214 thatstores pixel data for transmission to the display 210. The displaycontroller 206 continues transmitting this data to the display 210 untilthe amount of data in the buffer 214 is lower than a threshold. In someexamples, the threshold is an amount of data that accounts for thelatency in powering up the memory 202 and data fabric 204 to refill thebuffer 214. Once the amount of data in the buffer 214 is below thethreshold, the display controller 206 requests the data fabric 204 andmemory 202 to be powered up (e.g., via the power state controller 208).In response, the data fabric 204 and memory 202 power up. The displaycontroller 206 fetches pixel data from the memory 202 and places thatpixel data into the buffer 214. After the amount of pixel data in thebuffer 214 is above a threshold (e.g., when the buffer 214 is full or atsome other high value), the display controller 206 informs the powerstate controller 208 that the memory 202 and data fabric 204 do not needto be powered up any longer, and the power state controller 208 powersthose elements down in response. The display controller 206 continuestransmitting pixel data to the display 210 so that the display 210 cancontinue display frames. In sum, the stutter mode is one in which thedisplay controller 206 transmits display data to the display 210,powering the data fabric 204 and memory 202 on when necessary and offwhen not needed.

In some examples, the “stutter frequency” — the rate at which the datafabric 204 and memory 202 are powered up and down — is fast relative tothe display refresh rate (the frequency with which frames are displayedon the display 210). In an example, the buffer 214 is capable of storinga few display lines and thus must be refilled several times per frame.

FIG. 3 is a block diagram of the display controller 206 illustratingadditional detail. The display controller 206 includes multiple displaypipes 302. Each display pipe 302 includes, without limitation, screendata transfer logic 304 and a buffer 306. The screen data transfer logic304 transfers data from the buffer 306 to an associated display 210. Thebuffer 306 stores pixel data for the screen data transfer logic 304 totransmit to the display 210. In some examples, each display pipe 302 iscapable of operating in a “stutter mode” as described elsewhere herein,where much of the device 200 is powered down and where the display pipe302 wakes the data fabric 204 and memory 202 as needed to replenish thebuffer 306.

Each display pipe 302 is configured to transmit pixel data to adifferent display 210 when such a display 210 is connected to the device200. In one example, an operating system is set up to spread a desktopacross four displays 210. Each display pipe 302 provides pixel data forthe portion of the desktop appropriate for that display 210. In thismode of operation, the display pipes 302 operate concurrently, eachtransmitting data to the associated display 210 during the appropriatedisplay period.

FIG. 4 is a block diagram that illustrates the display controller 206operating in an expanded buffer mode, according to an example. In theexpanded buffer mode, one or more display pipes 302 are not providingpixel data to a display 210. In various examples, no display 210 ispresent for such display pipes 302, or a display 210 is present butdisabled, either by software or by hardware.

Because one or more display pipes 302 are not active, the screen datatransfer logic 304 associated with those display pipes 302 is nottransmitting pixel data for transmission to a display 210 associatedwith those display pipes 302. Thus the buffers 306 of those displaypipes 302 are available for use by the display pipes 302 that areactively transmitting data to a display 210. For this reason, in themode of operation in which one or more display pipes 302 are inactive, adisplay pipe 302 that is active uses buffers 306 from more than onedisplay pipe 302 to service a display 210.

More specifically, in this mode of operation, an active display pipefetches data from the memory 202 via the data fabric 204 into a buffer306 associated with that display pipe 302 and also into at least onebuffer 306 that is associated with a different display pipe 302 that isinactive (not transmitting pixel data to a display 210 associated withthat different display pipe 302). The active display pipe 302 transmitsdata from both the buffer 306 associated with that display pipe 302 andthe buffer associated with the inactive display pipe 302 to the display210. In response to the amount of data in the buffers 306 being below athreshold, the active display pipe 302 fetches additional pixel datafrom the memory 202 and data fabric 204 and stores that pixel data inthe buffers 306.

In some situations, such as where much of the device 200 is powered downand one or more display pipes 302 are inactive, the stutter technique isused with the technique in which one display pipe 302 uses multiplebuffers 306. In such a scenario, the active display pipe 302 operates inthe following manner. During a time period in which the memory 202 andthe data fabric 204 are powered down, the display pipe 302 transmitsdata from both the buffer 306 associated with that display pipe 302 andthe buffer 306 associated with an inactive display pipe 302 to thedisplay 210. In response to the active display pipe 302 detecting thatthe amount of data in these buffers 306 is less than a threshold, theactive display pipe 302 begins a sequence of operations to fetchadditional data from the memory 202.

In some examples, detecting that the amount of data in these buffers 306is less than a threshold includes determining that the amount of data inat least one of the buffers 306 is less than a threshold. In otherwords, in some examples, the threshold is a per-buffer threshold. Inother examples, detecting that the amount of data in these buffers 306is less than a threshold includes determining that the total amount ofdata in all buffers 306 that the active display pipe 302 is using totransmit pixel data to the display 210 is less than a threshold. Inother words, in some examples, the threshold is a total threshold,rather than a per-buffer threshold.

The sequence of operations to fetch additional data from the memory 202includes the active display pipe 302 requesting that the memory 202 anddata fabric 204 be woken up. In some examples, the active display pipe302 requests the power state controller 208 to power up the memory 202and data fabric 204. In response to these requests, the memory 202 anddata fabric 204 power up, changing from a low power state in which thememory 202 and data fabric 204 are not able to service read requestsfrom the active display pipe 302 to a higher power state in which thememory 202 and data fabric 204 are able to service read requests fromthe active display pipe 302.

Once the memory 202 and data fabric 204 are woken up, the active displaypipe 302 reads additional data from the memory 202 and places thatadditional data into one or more of the buffers 306 as needed. When theone or more buffers 306 are considered sufficiently full, the activedisplay pipe 302 informs the power state controller 208 that the memory202 and data fabric 204 no longer need to be powered on for the purposesof the active display pipe 302. In response, the power state controller208 powers down the memory 202 and the data fabric 204 in the event thatthose elements are not needed to be powered up for any other purpose. Inthe event that the memory 202 and data fabric 204 are needed forpurposes other than the active display pipe 302, the power statecontroller 208 does not power those elements down. The active displaypipe 302 continues reading pixel data from the one or more buffers 306and transmitting that data to the display 210 during the aboveactivities.

In some examples, the device 200 switches between a mode in which adisplay pipe 302 accesses only one buffer 306 (i.e., the buffer 306associated with that display pipe 302) and a mode in which the displaypipe 302 accesses multiple buffers 306, in transmitting data to one ormore displays 210. In some such examples, the device 200 is operating ina mode in which each display pipe 302 is coupled to a different display210 and is actively transmitting pixel data to the coupled display.Subsequently, one or more of the displays 210 stops needing data from adisplay pipe 302, due to, for example, becoming disconnected or powereddown. In response to the one or more displays 210 no longer needingdata, one of the display pipes 302 coupled to a display 210 that stillneeds pixel data begins utilizing at least one additional buffer 306 fortransmitting data to the associated display 210. For example, inresponse to a first display 210 coupled to a first display pipe 302being powered down or disconnected from the device 200, a first displaypipe 302 providing pixel data to that first display 210 stops providingpixel data to that first display 210. A second display pipe 302 stillcoupled to and providing pixel data to a second display 210 utilizes thebuffer 306 of the first display pipe 302, in addition to the buffer 306of the second display pipe 302, to provide pixel data to the seconddisplay 210. In some examples, after the first display pipe 302 againbegins providing pixel data to the first display 210, the second displaypipe 302 no longer uses the buffer 306 of the second display pipe 302 toprovide data to the second display 210.

In some modes of operation, the device 200 is not operating more thanone display 210. In such situations, the device does not alternatebetween a mode in which a buffer 306 is used by one display pipe 302 anda mode in which the buffer 306 is used by a different display pipe 302.However, in such situations, the display controller 206 contains buffers206 for multiple display pipes 302. Although each such display pipe 302is capable of transmitting data to an individual display 210, only onesuch display pipe 302 is active. In such situations, that display pipe302 uses the buffers 206 of each of the display pipes to transmit pixeldata to the display 210. In some modes of operation, multiple displays210 are coupled to the device 200 and are active, and thus some displaypipes 302 are actively providing data to those displays 210. However,not every display pipe 302 is active because the number of displays 210active and coupled to the device 200 is smaller than the number ofdisplays 210 supported by the device 200. In such situations, at leastone of the active display pipes 302 uses at least one of the buffers 306of the inactive display pipes 302.

The device 200 is capable of switching between any of the modes ofoperation described elsewhere herein. For example, the device 200 iscapable of switching between a mode of operation in which a singledisplay 210 is coupled to the device 200 and one display pipe 302 isusing all buffers 206 to transmit data to the single display 210, and amode of operation in which multiple displays 210 are coupled to thedevice 200 and all display pipes 302 use only their buffer 206 and notother buffers 206 to transmit pixel data to the coupled display 210. Inaddition, the device 200 is capable of switching between various modesin which different numbers of displays 210 are coupled and theassociated display pipes 302 are actively transmitting to those displays210. A display hot-plug event can trigger a change in the buffer 306allocation.

One benefit of allowing a display pipe 302 to use buffers 306 of otherdisplay pipes 302 is that the display pipe 302 does not need to wake upthe memory and data fabric 204 as often as if fewer buffers 306 wereused. By reducing the amount of time these elements are powered up andalso reducing the number of times these elements are switched betweenbeing powered up and powered down, an overall power reduction isachieved. In FIG. 4 , display pipe 302(2), display pipe 302(3), anddisplay pipe 302(4) are not providing data to any display 210. Displaypipe 302(1) is thus able to use all of the buffers 306 of the displaypipes 302 to transmit data to the display 210. In the event that thetechnique disclosed herein is combined with a pixel compressiontechnique, the amount of data available for a display pipe 302 isincreased even further, thus further reducing the amount of time thatthe memory and data fabric 204 are woken up.

FIG. 5 is a flow diagram of a method 500 for operating a displaycontroller, according to an example. Although described with respect tothe system of FIGS. 1-4 , those of skill in the art will understand thatany system, configured to perform the steps of the method 500 in anytechnically feasible order, falls within the scope of the presentdisclosure. The method 500 is described in the context of a system thatincludes at least two displays.

The method 500 begins at step 502, where a display controller 206transmits data in a first buffer to a first display that is coupled tothe display controller 206. The first buffer is a buffer 306 that isassociated with a first display pipe 302, which is a portion of thedisplay controller 206. The first display pipe 302 is a display pipethat transmits data to a display through an output coupled to the firstdisplay pipe 302 when such a display exists and is active. This “output”is a port coupled to the display pipe 302 that can be coupled to adisplay. Each display pipe 302 has such an output for connection to arespective display 210. The “association” between the buffer 306 and thefirst display pipe 302 means that, in a mode of operation in which thedisplay controller 206 is driving the maximum number of displays 210(the “max-displays mode”) that can be driven by the display controller206, the first buffer is the buffer from which data is transmitted tothe display associated with the first display pipe 302. The buffers 306within the display pipes 302 in FIG. 4 are buffers 306 associated withthose display pipes 302.

At step 504, the display controller 206 transmits pixel data from asecond buffer 306 that is associated with a second display pipe 302 tothe first display 210. The second buffer 306 and second display pipe 302are used to transmit data to a display coupled to the display pipe 302when such a display is present and enabled, but at step 504, such adisplay is not present or enabled. Thus the first display pipe 302 isable to use the second buffer 306 to transmit data to the first display210.

At step 506, the display controller 206 requests wake up of an externalmemory. In some examples, the external memory is the memory 202, whichis a general purpose of the device 200. In some examples, the displaycontroller 206 also requests wake up of the data fabric 204, whichcommunicatively couples the memory 202 to the display controller 206. Insome examples, a different element, such as the power state controller208 or a different element, initiates wake-up of the memory 202, insteadof the display controller 206.

At step 508, the display controller 206 fetches data from the memory 202and refills one or both of the first buffer 306 and the second buffer306. The data used to refill these buffers is additional data fortransmission to the display 210, such as additional pixels for thecurrent frame or for a subsequent frame. In some situations, after thisrefill, the display controller 206 or other element requests that thememory 202 and/or data fabric 204 be returned to a powered-down state.In some examples, the power state controller 208 returns these elementsto the powered-down state in the event that these elements are notneeded for a different element of the device 200.

It should be understood that many variations are possible based on thedisclosure herein. Although features and elements are described above inparticular combinations, each feature or element can be used alonewithout the other features and elements or in various combinations withor without other features and elements. In an example, although displaypipes 302 are shown with similar components, it is possible for one ormore display pipes 302 to include components not included in otherdisplay pipes 302. In an example, one or more display pipes includescomponents capable of filling its own buffer 306 and the buffer 306 ofone or more other display pipes 302 from memory. In another example, oneor more display pipes 302 includes components capable of requestingwake-up of the external memory in order to refill one or more buffers306. In another example, the buffers 306 for all display pipes are asingle buffer that is divided between the display pipes 302. In such anexample, the buffer is proportionally divided between active displaypipes 302 (where active display pipes are display pipes 302 that areproviding pixel data to a display).

The various functional units illustrated in the figures and/or describedherein (including, but not limited to, the processor 102, the inputdriver 112, the input devices 108, the output driver 114, the outputdevices 110, the data fabric 204, the display controller 206, the powerstate controller 208, the additional logic 212, the display pipes 302,and the screen data transfer logic 304) may be implemented as a generalpurpose computer, a processor, or a processor core, or as a program,software, or firmware, stored in a non-transitory computer readablemedium or in another medium, executable by a general purpose computer, aprocessor, or a processor core. The methods provided can be implementedin a general purpose computer, a processor, or a processor core.Suitable processors include, by way of example, a general purposeprocessor, a special purpose processor, a conventional processor, adigital signal processor (DSP), a plurality of microprocessors, one ormore microprocessors in association with a DSP core, a controller, amicrocontroller, Application Specific Integrated Circuits (ASICs), FieldProgrammable Gate Arrays (FPGAs) circuits, any other type of integratedcircuit (IC), and/or a state machine. Such processors can bemanufactured by configuring a manufacturing process using the results ofprocessed hardware description language (HDL) instructions and otherintermediary data including netlists (such instructions capable of beingstored on a computer readable media). The results of such processing canbe maskworks that are then used in a semiconductor manufacturing processto manufacture a processor which implements features of the disclosure.

The methods or flow charts provided herein can be implemented in acomputer program, software, or firmware incorporated in a non-transitorycomputer-readable storage medium for execution by a general purposecomputer or a processor. Examples of non-transitory computer-readablestorage mediums include a read only memory (ROM), a random access memory(RAM), a register, cache memory, semiconductor memory devices, magneticmedia such as internal hard disks and removable disks, magneto-opticalmedia, and optical media such as CD-ROM disks, and digital versatiledisks (DVDs).

What is claimed is:
 1. A method for use in a display system, comprising:operating in a dual pipe mode of operation in which each display pipetransmits data from a respective buffer to an associated display, themode comprising: transmitting data in a first buffer associated with afirst display pipe to a first display associated with the first displaypipe via the first display pipe; and transmitting data in a secondbuffer associated with a second display pipe to a second displayassociated with the second display pipe via the second display pipe. 2.The method of claim 1, further comprising: entering into the dual pipemode of operation in response to detecting connection or enablement ofthe second display.
 3. The method of claim 1, further comprising:operating in a single display mode of operation in which one displaypipe transmits data from a plurality of buffers to an associateddisplay, the mode comprising: transmitting data in the first bufferassociated with the first display pipe and the second buffer associatedwith the second display pipe to the first display via the first displaypipe.
 4. The method of claim 3, further comprising: entering into thesingle display mode of operation in response to detecting disconnectionor powering down of the second display.
 5. The method of claim 1,further comprising: requesting wake-up of a memory; and refilling one orboth of the first buffer and the second buffer from the memory.
 6. Themethod of claim 5, wherein requesting wake-up of the memory is done inresponse to an amount of pixel data in one or both of the first bufferor the second buffer being below a threshold.
 7. The method of claim 5,further comprising: after refilling the one or both of the first bufferand the second buffer, requesting the memory be powered down.
 8. Themethod of claim 7, further comprising: in addition to requesting wake-upof the memory, waking up a data fabric.
 9. The method of claim 8,further comprising: after refilling the one or both of the first bufferand the second buffer, requesting the data fabric be powered down.
 10. Adisplay system, comprising: a display controller; a first display pipeof the display controller, the first display pipe including a firstbuffer; and a second display pipe of the display controller, the seconddisplay pipe including a second buffer, wherein the display controlleris configured to operate in a dual pipe mode of operation in which eachdisplay pipe transmits data from a respective buffer to an associateddisplay that includes: transmitting data in the first buffer associatedwith the first display pipe to a first display associated with the firstdisplay pipe via the first display pipe; and transmitting data in thesecond buffer associated with the second display pipe to a seconddisplay associated with the second display pipe via the second displaypipe.
 11. The display system of claim 10, wherein the display controlleris further configured to enter into the dual pipe mode of operation inresponse to detecting connection or enablement of the second display.12. The display system of claim 10, wherein the display controller isfurther configured to operate in a single display mode of operation inwhich one display pipe transmits data from a plurality of buffers to anassociated display that includes: transmitting data in the first bufferassociated with the first display pipe and the second buffer associatedwith the second display pipe to the first display via the first displaypipe.
 13. The display system of claim 12, wherein the display controlleris further configured to enter into the single display mode of operationin response to detecting disconnection or powering down of the seconddisplay.
 14. The display system of claim 10, wherein the displaycontroller is configured to: request wake-up of a memory; and refill oneor both of the first buffer and the second buffer from the memory. 15.The display system of claim 14, wherein requesting wake-up of the memoryis done in response to an amount of pixel data in one or both of thefirst buffer or the second buffer being below a threshold.
 16. Thedisplay system of claim 14, wherein the display controller is furtherconfigured to: after refilling the one or both of the first buffer andthe second buffer, request the memory be powered down.
 17. The displaysystem of claim 14, wherein the display controller is further configuredto: in addition to requesting wake-up of the memory, wake up a datafabric.
 18. The display system of claim 17, wherein the displaycontroller is further configured to: after refilling the one or both ofthe first buffer and the second buffer, request the data fabric bepowered down.
 19. A display system, comprising: a first display; adisplay controller; a first display pipe of the display controller, thefirst display pipe including a first buffer; and a second display pipeof the display controller, the second display pipe including a secondbuffer, wherein the display controller is configured to operate in asingle display mode of operation in which each display pipe transmitsdata from a respective buffer to an associated display that includes:transmit data in the first buffer associated with the first display pipeand the second buffer associated with the second display pipe to thefirst display via the first display pipe.
 20. The display system ofclaim 19, further comprising a second display, wherein the displaycontroller is configured to operate in a dual pipe mode of operation inwhich each display pipe transmits data from a respective buffer to anassociated display that includes: transmitting data in the first bufferassociated with the first display pipe to the first display associatedwith the first display pipe via the first display pipe; and transmittingdata in the second buffer associated with the second display pipe to thesecond display associated with the second display pipe via the seconddisplay pipe.